The present invention relates to a circuit or device that includes over-voltage and/or short circuit protection. In particular the present invention relates to an apparatus for protecting a device against an over-voltage condition that is in excess of its breakdown voltage. The device may include a transmitter and/or a receiver of data on a data line such as a universal serial bus (USB).
USB specifications require that a short circuit of a data line (DP/DM) of a USB module with a power supply line should be withstood. With shrinking process geometries, thin gate oxides used in current CMOS fabrication technologies are not able to withstand this over-voltage. Therefore, special protection schemes need to be employed.
Some prior art schemes rely on clamping diodes to limit voltages on data lines. The diodes are chosen to clamp any voltage above a stress limit of transistors used in an associated circuit and thereby protect the circuit. Clamping diodes are often implemented as part of ESD (electrostatic discharge) management circuits, which cause large current flows under short circuit conditions. Moreover, since Zener diodes are not available in conventional CMOS technologies, clamping diodes usually require off-chip components increasing product costs.
Other prior art schemes rely on high current drainage especially in a transmitter driver stage, such that a high voltage is never present across any device. However these schemes result in performance compromises and complexities due to additional layout considerations and higher parasitics. The prior art schemes also rely on a continuous supply of power being present for the protection schemes to be effective in the absence of which they fail to protect the devices.
FIG. 1 shows a prior art system using clamping diodes to limit voltage on data lines associated with a circuit. The diodes are chosen such that they clamp any voltage above the stress limit of transistors used in the circuit and thereby protect the circuit. This is either implemented as part of ESD circuits, which causes a large current flow in short conditions, or requires off-chip components since Zener diodes are not present in conventional CMOS technologies, thereby increasing cost.
FIG. 2 shows a prior art transmitter circuit that relies on high current drainage in an over-voltage condition especially in the transmitter driver stage, such that a high-voltage is never seen across any of the devices. For example, assuming 3.3V devices are used, if the data line (DP/DM) is shorted to 5V and Vdda is 3.3V, the pull-down path is turned off and protected by applying the voltages,                C=Vdda (3.3V)        D=0VThe pull-up path is protected by applying the voltages,        A=Vdda (3.3V)        B=Vdda (3.3V)        
For the pull-up, there is a constant current drain through the body and the channel of the PMOS device, which may be as high as 150-200 mA. Due to voltage drop across Rprotect, no device sees more than the breakdown voltage across it. This prior art scheme requires additional layout considerations and may lead to performance compromises because of higher parasitics. This scheme also has a disadvantage because if during a short circuit condition, the power Vdda falls to 0, it fails to protect the devices (NMOS with gate connected to C) in its absence.
It would be advantageous to have a short circuit and/or over-voltage protection scheme that does not depend on the presence of a power supply. This may be important for self-powered devices that switch off the supply until a USB session is required. It would also be advantageous to have a protection scheme that does not require special devices such as Zener diodes. It would also be advantageous to have a protection scheme that does not require excessive current drainage during a short circuit avoiding strain on layout and other performance criteria. It would also be advantageous to have a protection scheme that may be readily implemented with current CMOS manufacturing technologies.